Reliability Challenges In 16nm FinFET Design

As the IC industry rapidly adopts the 16nm technology node, IC designers are faced with a new wave of reliability challenges. The 16nm node has introduced several changes in the way that the devices are fabricated and how the metal stack-up is built. On one hand designers gain speed, leakage and density improvements. On the other, reliability engineers need to address the narrowing electromigration margins and electrostatic discharge design challenges.

What is new in 16nm FinFET Technology?
The 16nm FinFET device is a game changer in every aspect of design. A traditional planar transistor has two dimensions — the width and length of the gate — that control the I-V characteristics of the device. The traditional formula of either increasing the width or decreasing the length of the device can enhance the current drive capability, thereby increasing the speed of the device. The 16nm FinFET device adds a third dimension to device geometry, the ‘fin height’. Without increasing planar area, the current drive capability of a transistor can be increased by adjusting the ‘fin height’ and number of fins.

The gate terminal of the FinFET device also has better electrostatic control over the channel, resulting in off-state leakage improvements. This combination of reduced leakage and increased drive capability has provided a tremendous advantage in performance for 16nm node designs.

Impact on Electromigration (EM)
The increase in current density per unit area for the 16nm node has brought its share of reliability verification hurdles. It is common to see an average of 25% increase in drive current with these devices. As more current flows through the same metal interconnects, the margins for EM becomes smaller and meeting the Mean Time to Failure (MTTF) requirements more challenging. Not only are the EM limits smaller, but the EM rule complexity has also increased. New types of EM rules that are dependent on the direction of current flow, metal topology, via types, co-vertical metal overlaps etc. are now required for accuracy.

Impact on Electrostatic Discharge (ESD)
Another reliability verification challenge with the 16nm node is ESD protection. The increased current density and joules self-heat generated during an ESD event makes the ESD protection devices less efficient than their planar counterparts. Snap-back type ESD devices are also difficult to fabricate in the 16nm node, increasing the re-design cost of ESD schemes. The ESD design window is between the voltage above the normal device operation and the voltage below the device breakdown. Compared to the planar devices, the breakdown voltages for FinFETs are much lower, thereby decreasing the ESD operating window. This requires ESD designers to use simulation driven approach to accurately place diodes and clamps in their ESD schemes. Also in the past few technology nodes, there has been an interesting trend in the failure mechanism during an ESD event. Interconnect failure or metal burn-out due to current crowding is a major cause for ESD failures. Performing current density checks as part of an ESD design process accurately identifies and resolve the current bottlenecks and ensures interconnect safety during an event.

Figure-1: ESD failure types and cost of re-design

Impact on Thermal
Several studies indicate that the heat generated in the 16nm FinFET process is a bigger problem than in the planar transistors. Heat escape pathways for the fins in the FinFET devices are not as good as in the planar devices. Along with the poor escape pathways, the higher current density further exacerbates the joules self-heating problem. For planar transistors the heating of the substrate can easily be modeled as an averaged phenomenon. But for the FinFET devices there is a higher localization of heat source that needs to be accurately modeled for correct thermal distribution. The Mean Time to Failures (MTTF) for metal interconnects also has an inverse exponential dependence on temperature. Understanding and simulating the thermal impact on EM for metal interconnects is mandatory with this technology.

Figure-2: Key reliability challenges in 16nm node

Library and IP Design Challenges
Scaling from one technology node to another was usually a matter of shrinking geometries and handling new Design Rules Checks (DRC) rules based on foundry requirements. However, with the 16nm node, libraries and IPs need to be significantly redesigned to meet reliability requirements on EM and ESD. For example, EM on standard cells needs to be simulated for proper binning of frequency and load characteristics using a simulation based approach. With the increased current densities at 16nm nodes, standard-cells need to be carefully analyzed for EM failures for different load conditions.

Conclusion
As we scale technology nodes into the sub-10nm range, the reliability verification requirements will grow exponentially. Reliability simulations will need to use correct workloads, simulate transient phenomenon and incorporate real boundary conditions in order to capture proper failure mechanisms. Average analysis for modeling EM and thermal simulations can no longer represent true behavior in these advanced technology nodes. With decreasing breakdown voltages and parasitic discharge pathways, ESD design and verification will become more complex than they are today. EDA vendors must deliver advancements in their tools that can address these reliability challenges, including those that will be faced by future technologies such as 3D-ICs.